Integrated circuit devices typically include a number of circuit elements, including active elements, such as transistors, and sometimes passive elements, such as resistors and capacitors formed in an integrated circuit substrate. In operation, an integrated circuit substrate can be subject to unplanned current injection events that can adversely affect the operation of the circuits.
For example, the potential of external signal paths connected to integrated circuits pins may briefly drop below an ideal low supply voltage. Integrated circuit pins may also be referred to as pads. This brief drop, sometimes called undershoot, may cause the interface signal to drop below the ideal low voltage supply. Undershoot can be caused by a number of factors, including mismatch between signal generator output impedance and signal receiver input impedance, transmission line mismatch, wiring inductance, power supply noise, and other causes.
In the case of an undershoot condition, current (in this case electrons) can be injected into the substrate of an integrated circuit. This injection can occur when reverse biased p-n junctions which normally isolate the substrate from external signals become forward biased due to the undershoot. The p-n junctions form diodes which conduct current in the forward biased condition and block current in the reverse biased condition. The p-n junctions connected to external signal interfaces in integrated circuits may be explicit diodes or inherent diodes formed from the junctions of other semiconductor devices. An example of a semiconductor device with inherent or parasitic diodes are field effect transistors (FETs) which typically use reverse bias to isolate the source and drain semiconductor materials from the substrate (also called body or bulk) semiconductor material.
The source and drain materials are usually the complement of the body or bulk, that is for an n-channel MOSFET, the body or bulk are typically p-type semiconductor material and the source and drain regions are formed with n-type semiconductor material. Regions of semiconductor material of the opposite doping of the surrounding material can be called a diffusion region(s) or simply diffusion. The source and drain regions of a FET may be called source or drain diffusion or source drain junctions. The term diffusion can mean any means of introducing impurities (doping) into silicon to obtain n-type or p-type material, including but not limited to diffusion and ion-implantation. Junction can refer to the p-n interface of a semiconductor, but is also commonly used to refer to source or drain regions of MOSFET devices.
The current injected into the substrate may disturb the normal operation of a semiconductor device. In particular, circuit nodes that are not strongly maintained at desired potentials can have their potential affected by the substrate currents. More particularly, the substrate current can cause undesired current to flow in nearby reverse biased p-n junctions. These undesired currents can affect the potential of nodes which are not strongly driven to the desired potential. High impedance nodes such as those using high resistance pull-up or pull-down resistors are examples of nodes which are not strongly driven to the desired potential. The undesired current can change the desired voltage of the high-resistance node. In the case of a node with a high value resistor, the error voltage may be the resistor value in ohms multiplied by the undesired current.
A very particular example of unwanted current injection effects, as related to an electrostatic discharge (ESD) protection circuit, will now be described.
Typically, integrated circuit devices (i.e., chips) have interface pads which connect to external signals and that include protection against ESD events. An ESD event can include the transfer of a significant amount of electrical energy to an integrated circuit interface pad in a very short time (usually tens to hundreds of nanoseconds). The integrated circuit must be capable of dissipating the energy from the ESD event to prevent damage to devices contained in the integrated circuit. ESD protection systems are usually implemented on integrated circuits to provide ESD protection. More specifically, the integrated circuit must be able to conduct the current from the ESD event while limiting the potential on the integrated circuit to values that do not cause damage. The integrated circuit must also be able to dissipate both the peak power and energy of the ESD event. The respective external interface pad subject to the ESD event can be referred to as the “zapped” pad.
Various conventional approaches to ESD protection are known. One method can be to use “snapback” devices. Such an approach can rely on bipolar devices including junction transistors (BJTs) and thyristors which are inherent in most semiconductor integrated circuits and are formed from p-n junctions. These bipolar devices can include those devices normally considered to be parasitic devices in technologies that use field effect transistors such as complementary metal-oxide-semiconductor (CMOS) based integrated circuits. During an ESD event, the bipolar device can enter a conductive state, to thereby safely dissipate the ESD discharge. A drawback to such a conventional approach can be that parasitic bipolar devices can be difficult to control in actual implementation. The difficulty in controlling electrical parameters of these devices and the difficulty of modeling their behavior to allow simulating ESD protection networks makes it difficult to predict the ESD protection provided by these networks. The lack of predictability can lead to inferior ESD performance, or over designed networks which are large, or both. In addition, such approaches can consume relatively large amounts of silicon area.
A second conventional approach to ESD protection can be an actively switched network. A control circuit is used to activate the turn on of devices to conduct the ESD current through an actively switched network. The control circuit should be capable of differentiating between normal operation and an ESD event. The control circuit which detects the ESD event is commonly called a trigger circuit. As compared to a conventional method using snapback devices, this switched ESD network method can be simulated using conventional circuit simulators, resulting in more predictable protection from ESD discharges.
A conventional trigger circuit may contain nodes not strongly driven to the desired potential. These nodes exist to control generation and timing of the signals which activate the switched ESD network. In normal operation, these nodes are expected to remain at the desired potential to prevent “false triggering” or activation of the ESD network during normal device operation. The substrate current previously described can be present in the area of the ESD trigger circuit, and can cause “false triggering” in conventional trigger circuits during normal device operation.
Activating the ESD network under normal operating conditions results in excessive power consumption, may cause the integrated circuit to fail to operate as intended, and may cause permanent damage to the integrated circuit.
Referring now to FIG. 5, a conventional actively switched ESD protection network is shown in a block schematic diagram and designated by the general reference character 500. For simplicity of description, conventional network 500 shows protection for a single interface pad.
FIG. 5 shows an interface pad 502 which may experience an ESD discharge (an ESD event). The interface pad 502 may be connected to ESD protection diodes D1 and D2. These diodes may be explicit or parasitic diodes formed by the drain junctions of MOSFET transistors. Such diodes can ensure that a current path during an ESD event conducts current away from interface pad circuitry that is to be protected. A conventional network 500 can also include a high voltage power supply bus 504, as well as a low voltage power supply bus 506.
Conventional ESD network 500 further includes trigger circuit 508 with corresponding current switch 510. Trigger circuit 508 can act as an ESD event detector that generates a pulse “trig_out” of a predetermined width at the output 512 in an ESD type event. More particularly, if a slew rate at high voltage power supply bus 504 (and implicitly the slew rate of a respective zapped pad) exceeds a certain value, the event can be considered an actionable ESD event and a pulse can be output by the trigger circuit 508 detecting the event.
Accordingly, in FIG. 5, trigger output signal trig_out can control one or more current switches 510 connected between a high voltage power supply node (e.g., pad) 504 and a low voltage power supply node (e.g., pad) 506. The current switch 510 can also be called a shunt or a clamp. In metal oxide semiconductor technologies, it is often implemented as an insulated-gate field effect transistor.
A basic operation of conventional network 500 during a typical ESD event will now be described. In the example described, it is assumed that a zapped pad is 502, with the ESD energy being applied with respect to the low voltage power supply, now referred to as ground.
In such an event, an ESD event can occur at an interface pad 502. An ESD discharge resulting from the event is transferred from the zapped pad 502 to high voltage power (Vcc) supply bus 504 via diode D1, causing the Vcc potential at bus 504 to rise quickly.
Provided the ESD event causes a sufficiently high slew rate on Vcc bus 504, one or more trigger circuits 508, powered by the Vcc bus 504, can detect the ESD event and turn on corresponding current switch 510 connected directly across supply buses 504 and 506. Such an enabled current switch 510 can serve as an ESD clamp and route ESD current from high voltage power supply bus 504 to low voltage power supply bus 506, and thus away from sensitive circuits.
By routing ESD current from high voltage power supply bus 504 to low voltage power supply bus 506 the enabled current switch 510 clamps or limits the voltage between power supply busses 504 and 506. The clamped voltage between power supply busses 504 and 506 is the enabled resistance of the ESD current switch 510 multiplied by the ESD current passing through switch 510 and any supply bus voltage drop. Such a clamping action can also limit on-chip voltages during ESD events. This clamping limits the voltage at the interface pad to prevent damage to circuitry connected to the interface pad (typically inputs, outputs, or both), and also protects other internal circuits of the integrated circuit by limiting internal voltages.
While a trigger circuit 508 is expected to operate in response to a high slew rate (e.g., ESD) event, ideally, such circuits should not trigger during normal functional mode. If such circuits are activated during a normal mode of operation, supply noise can be created, which can adversely affect the performance of the integrated circuit. As but two examples, in the case of a memory device, such supply noise can affect data access times, and in the case of a communication device, create output jitter. Furthermore, excessive power supply current would be required to operate the device as extra current would flow through the ESD switches from the high voltage to the low voltage supply busses. Still further, such a large amount of current can result in permanent device damage.
Unfortunately, some conventional trigger circuits can be susceptible to triggering in a functional mode due to unplanned current injection. One example of such a conventional trigger circuit is shown in a schematic diagram in FIG. 6, and designated by the general reference character 600. A conventional trigger circuit 600 can include a slew rate detector 602, a pulse generator 604, and an output driver 606. A slew rate detector 602 can be an RC differentiator that includes a capacitor C60 and resistor R60 connected in series between an ESD bus 608 and a low power supply bus 610. If an ESD event is translated to ESD bus 608, a slew rate detector 602 can output a signal Vtrip that can have a voltage approximately proportional to an ESD bus 608 voltage (Vtrig) slew rate and the RC time constant of the RC differentiator, as expressed below:Vtrip=R*C*d(Vtrig)/dt where R is the resistance of R60 and C is the capacitance of C60.A pulse generator 604 can include a voltage level detector implemented with an n-channel metal-oxide-semiconductor (MOS) transistor M60 and a pulse extender implemented with a parallel RC circuit formed by resistor R62 and capacitor C62. According to such a structure, an RC time constant of slew rate detector can be adjusted. Accordingly, during an ESD event the following can hold:R*C*d(Vtrig)/dt>=Vth (of M60).In such a case, transistor M60 can be turned on, and by operation of pulse extender R62,C62, a voltage can be generated between a sense node 612 and ESD bus 608.
During an event determined not to be an actionable ESD event, the following can hold:R*C*d(Vtrig)/dt<Vth (of M60).In such a case, transistor M60 does not become active. Thus, no M60 drain current can be generated and a potential between sense node 612 and ESD bus 608 can remain at zero.
An output driver 606 can process an output of pulse generator 604 to generate a pulse signal trig_out that can activate shunting current source, or the like. In the conventional trigger circuit 600, if the magnitude of V(Vtrig, Vsense)>Vth (M62), a pulse can be generated at an output node 614, where V(Vtrig, Vsense) is the amount by which a potential at sense node 612 is less than that at ESD bus 608.
Ideally, only during an ESD event will a pulse be generated at output node 614.
However, the conventional trigger circuit 600 of FIG. 6 can exhibit false triggering due to injected substrate electrons. Such false triggering can be caused by a parasitic npn BJT 616. Such a BJT 616 can include one or more collectors including at least one formed by a drain diffusion of transistor M60, a base formed by a substrate of the integrated circuit that contains the bulk or body of transistor M60, and one or more emitters connected to semiconductor region into which electrons are injected. In the case of an npn transistor, such an emitter may be formed by n-type semiconductor material connected to interface pads, including diodes or MOSFET source or drain regions, which is surrounded by p-type semiconductor material. Parasitic BJT 616 may have one or more collectors formed by multiple diffusion junctions at various distances from the emitter. These collectors may affect more than one device or circuit.
More than one parasitic BJT 616 may be present. In general each region of n-type semiconductor material may act as an emitter if forward biased with respect to the surrounding p-type material, and each region of n-type semiconductor material reverse biased may act as a collector. While emitters connected to signals from external sources (that is, those emitters connected to interface pads) are more likely to be forward biased than signals generated within the integrated circuit, occasionally internally generated signals may also forward bias emitters.
A false triggering can occur in the absence of any ESD event when injected electrons result in a collector current (IC) of parasitic BJT 616 being large enough to meet the following condition:IC>=|Vth(M62)|/R62.Under such conditions, a voltage differential between ESD node 608 and node 612 can be large enough to turn on transistor M62, thus generating an active signal trig_out at output node 614. This can activate ESD current switches resulting in the integrated circuit drawing a large operating current (Icc).
The above false triggering can occur during normal operation of a conventional integrated circuit device. In particular, a conventional ESD trigger circuit, like that described above, can be included in an integrated circuit (IC). When such an IC is operating normally, unrelated to ESD events, the trigger circuit can trigger, turning on the ESD current switch and causing the integrated circuit to draw large amounts of current. More particularly, an external signal applied to an interface pad of the integrated circuit may cause a current to be injected into the substrate. This current may cause unintended currents within the trigger circuit, which activate the trigger and result in an undesirable “false trigger”.
Due to the potential for false triggering, conventional circuits may require large separation between sensitive circuits and junctions directly connected to interface pads. Such a situation is shown in FIG. 7. FIG. 7 is a top plan view of a portion of an integrated circuit 700 that shows a number of pads (one of which is shown as 702) each of which can include an area in which ESD protection circuits (one such area is shown as 704). Some circuits can be adversely affected by injection current. Accordingly, a circuit sensitive to injected substrate current (706), such as a trigger circuit, may require a minimum distance dmin from injection areas (704). The above assumes that the sensitive circuit 706 is located in close proximity to semiconductor junction that receives injected current. The restricted placement of the sensitive circuit with respect to junctions directly connected to interface can cause inefficient integrated circuit layout and larger, more expensive integrated circuits.
As but one example, a value dmin of greater than 200 microns may be required. The value dmin will depend on many factors including the efficiency of the injecting junction, the efficiency of guard rings and other substrate current collections mechanisms, the number, area and distance of unrelated current collecting junctions, and the sensitivity of the high-impedance node to injected current. Dmin is typically difficult to predict analytically and is usually found through trial and error.
FIG. 8 shows a side cross sectional view of a parasitic transistor formation. FIG. 8 shows how parasitic BJT 816 can be formed in a substrate 800 by one or more portions of n-channel MOSFET M60 and a diffusion region 802 connected to an interface pad 818 for injecting current.
In light of the above, it would be desirable to arrive at some way of addressing changes in transistor performance resulting from substrate current injection events.
It would also be desirable to arrive at an ESD trigger circuit that is not as susceptible to false triggering due to current injection as a conventional approach, like that of FIG. 6.